[ Cadence ] Cadence Reference Flow with Digital and Signoff Tools Certified on Samsung’s 10nm Process Technology

작성자
nlt_admin
작성일
2017-01-09 13:39
조회
570
Reference flow enables system and semiconductor companies to accelerate delivery of designs on Samsung’s second-generation 10nm process (10LPP)

SAN JOSE, Calif., 24 Oct 2016


Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its complete suite of digital and signoff tools has been certified for Samsung Electronics’ Process Design Kit (PDK) and Foundation Library on Samsung’s second-generation of 10nm LPP (Low Power Plus) process. Samsung also validated the Cadence® reference flow using a quad-core design with the ARM® Cortex®-A53 processor on the 10LPP process, which was implemented with the low-power design methodology covering power-gating and memory retention, IEEE 1801 UPF2.1 power intent, and statistical on-chip variation (SOCV)-based timing closure using the Liberty Variation Format (LVF) library.


The Cadence digital and signoff tools met all of Samsung’s accuracy requirements, enabling foundry customers to quickly achieve design closure and deliver large, complex FinFET designs faster with the 10LPP process. In addition, the Cadence signoff tools have been certified for tapeout using Samsung’s certification criteria for baseline accuracy. The tools in the design flow include:

•Innovus™ Implementation System: Based on a massively parallel architecture, it enables larger designs and reduced turnaround time while supporting Samsung’s 10LPP design requirements, such as floorplanning, placement and routing with integrated color-/pin-access /variability-aware timing closure, and clock tree and power optimization

•Genus™ Synthesis Solution: Delivers improved productivity during register-transfer level (RTL) design and highly correlated, optimal quality of results (QoR) in final implementation

•Quantus™ QRC Extraction Solution: Offers best-in-class accuracy versus foundry baseline; faster, scalable cell-level and transistor-level extraction; multi-patterning; multi-coloring; and a built-in 3D extraction capability, Quantus Field Solver (FS)

•Conformal® Logic Equivalence Checking (LEC): Ensures the correctness of logic changes and engineering change orders (ECOs) as well as the implementation flow, while enabling the comparison of different views/abstraction levels

•Conformal Low Power: Enables the creation and validation of power intent in context of the design, combining low-power equivalence checking with structural and functional checks to allow full-chip verification of power-efficient designs

•Tempus™ Timing Signoff Solution: Provides integrated, advanced process delay calculation and static timing analysis (STA) that achieves Samsung’s accuracy requirements, including those at low voltage operation

•Voltus™ IC Power Integrity Solution: Cell-level power integrity tool that supports comprehensive electromigration and IR drop (EM/IR) design rules and requirements while providing full-chip system-on-chip (SoC) power signoff accuracy

•Physical Verification System: Includes advanced technologies and rule decks to support design rule checking (DRC), layout versus schematic (LVS), smart metal fill, yield scoring, voltage-dependent checks, and in-design signoff

•Litho Physical Analyzer: Enables designers to detect and automatically repair process hotspots to improve design manufacturability and yield of digital, custom and mixed-signal designs, libraries and IP. This is part of Samsung’s foundry DFM offering.

•Cadence CMP Predictor: Predicts the 3D topology variation and hotspots caused by chemical mechanical polishing (CMP) to improve design manufacturability and reduce topology variation. This is part of Samsung’s foundry DFM offering.

•LDE Electrical Analyzer: Allows layout-dependent effect- (LDE-) aware re-simulation, layout analysis, matching constraint checking, reporting on LDE contributions, and the generation of fixing guidelines from partial layout to accelerate analog design convergence

•Modus™ Test Solution: Provides scan and logic/memory built-in self test (BIST) insertion, combined with a new physically aware 2D Elastic Compression architecture, enabling design engineers to achieve reductions in test time to minimize production test cost

For more information on Cadence digital and signoff solutions, please visit https://www.cadence.com/content/cadence-www/global/en_US/home/solutions/advanced-node-solutions.html.

“Samsung and Cadence collaborated closely on this new 10LPP process reference flow to provide our mutual customers with a fast path to design closure,” said Jaehong Park, senior vice president of the Design Service Team at Samsung Electronics. “Cadence’s digital and signoff tools have implemented methodology innovations that enable designers to access and reap the benefits of our 10LPP process.”

“Samsung’s certification of the Cadence digital tools enables customers to manage and overcome complexity and deliver advanced 10LPP designs faster,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Customers using the Cadence flow on Samsung’s latest 10LPP process can also achieve optimal power, performance and area (PPA) to meet their aggressive time-to-market requirements.”