[ ClioSoft ] ClioSoft at DAC - Register for your demo!

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2019-04-30 13:07
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Join us at the 56th Design Automation Conference (DAC) in Las Vegas, NV in booth #927 to learn about our industry standard SoC design and IP management solutions that are tailormade for the semiconductor industry.

- SOS7 platform is the design collaboration system of choice for analog, RF, digital and mixed-signal designs at over 300 companies such as Analog Devices, Arm, Cadence, Google, Mediatek and TSMC.
- designHUB platform, launched two years ago, successfully enables companies in making IP reuse a reality within their enterprise.


Re-using Your IPs To Develop SoCs Faster

- What internal or 3rd party IPs are available for use within the company?
- How can I search and compare IPs, review their usage and resolve any questions with the IP developers prior to selecting an IP?
- Can I review the experience of other designers using this IP before using it?
- How can I track and prevent the unauthorized usage of 3rd party IPs?

The designHUB platform provides an IP reuse ecosystem where you can easily search for and compare IPs across your company independent of which data management platforms the IPs are located in. You can track the IP usage, review the IP quality and user experience before selecting the desired IP. While developing your SoC, see how you can collaborate with your fellow team members by using the project dashboard to keep the team in-sync and leverage the existing IP knowledgebase to resolve any IP issue in a timely manner. And upon completion, publish your SoC or parts of it into the IP repository with the desired access controls to prevent unauthorized usage.



Managing And Reusing Your Analog IPs Successfully
- Do you want to browse and compare IPs, track their usage, qualify them and then download a version of the IP into your workspace directly from the Cadence Virtuoso platform?
- Do you want to publish your design into the IP repository from Cadence Virtuoso with the desired access controls and track its usage throughout the company?
- Do you want to receive notifications on changes made to the IPs used in your project?

This demo will explain how to collaborate easily with different teams to develop and publish your analog IPs directly from the Cadence Virtuoso platform by using the designHUB ecosystem. You will learn how to create, manage and reuse the different versions of IPs for specific PDKs and foundries by using the designHUB platform while leveraging a live and growing knowledge base. See how your team can collaborate efficiently on their analog/mixed-signal designs and leverage internally developed resources – semiconductor IPs, flows, scripts, etc. – to build SoCs successfully within a shorter time.



Managing Your Designs For Successful Tapeouts
- Are you struggling with managing design data from multiple design flows across multiple design centers?
- Do you find it difficult to manage design handoffs between teams of your project?
- Are you spending too much time investigating changes made to the design or wondering whether you have the latest version of the design data?
- Are you blowing up your budget on network storage?

Learn how you can leverage the SOS7 design management platform, already in use by over 300 customers, for collaborating on all analog, RF, digital and mixed-signal designs, to increase their designer productivity and team efficiency. See how SOS7 enables you to manage your designs, track open issues, take snapshots of your design database and provides a non-intrusive way to manage your design handoffs between different teams. Take a look at the different ways SOS7 can keep your data secure and minimize your network storage space used for your project.



Managing Design Traceability For Automotive Electronics
- Do you want to trace the usage of this IP across your company?
- Which designs have been implemented using this version of the specification?
- Are you looking to identify the design modifications made since yesterday?
- Do you want to track what design changes were made to fix this bug?

Want to learn how you can track documents, IPs, issues and their fixes against the IP/SoC implementation? This is the demo for you. See how to view the open issues hierarchically for the IPs, be notified about the fixes, review what changed and track the usage across different SoC implementations. From a design module perspective, see how you can track the usage across different projects and view open issues associated with it or track the various documents and its revisions used during the implementation as well as the issues found against a requirement.



Visual Design Diff
- Does your design team struggle to identify modifications made to the schematic or layout by other team members?
- Are you having problems reviewing the changes in your schematic or layout during ECOs?

Learn to use Visual Design Diff (VDD) to graphically compare different versions of a schematic or layout and to quickly highlight the differences even when the schematic is modified by an RF designer.



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REQUEST DEMO : https://www.cliosoft.com/www2/marketing/tradeshows/dac/2019/demo/register/dacdemo.php