Cadence Extends Digital Design Leadership with Revolutionary ML-based Cerebrus ...

2021-07-23 10:36
SAN JOSE, Calif., 22 Jul 2021


Cerebrus uses unique ML technology to drive the Cadence RTL-to-signoff implementation flow, delivering up to 10X productivity and 20% PPA improvements for implementation
Built with a re-usable and transportable reinforced learning model that increases effectiveness with each use
Provides more efficient on-site and cloud compute resource management capabilities than traditional human-driven design exploration
Improves PPA and productivity across many nodes and multiple end-applications including consumer, hyperscale computing, 5G communications, automotive and mobile design
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the delivery of the Cadence® Cerebrus™ Intelligent Chip Explorer, a new machine learning (ML)-based tool that automates and scales digital chip design, enabling customers to efficiently achieve demanding chip design goals. The combination of Cerebrus and the Cadence RTL-to-signoff flow offers advanced chip designers, CAD teams and IP developers the ability to improve engineering productivity by up to 10X versus a manual approach while also realizing up to a 20% better power, performance and area (PPA).

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