The FPGA market is rapidly growing in the traditional Aero-Defense sector as well as in the emerging sectors like Automotive and IoT. FPGA design is considered relatively simple compared to the complexities posed by an SoC design, but FPGA verification is not that simple. Traditionally, companies have been using FPGA vendor tools, methodologies, and flows for verification, but this is proving to be insufficient due to the challenging requirements of quality and robustness. It is also inefficient, due to the slow simulation speed for large regression test suites. The quality and robustness thus cannot be compromised for mission-critical designs in Aero-Defense and Automotive spaces. Moreover, verification becomes challenging for FPGA to ASIC design flows due to increased complexity.

StreamDSP, a digital design company specializing in video processing and high-speed serial communications cores for FPGAs and ASICs, faced similar verification challenges for their FPGA-based designs for defense applications. In this blog, we will delve into the typical FPGA verification challenges and how StreamDSP was able to overcome them by easily migrating to Cadence Xcelium and thereby achieving 3X to 4X performance over other major simulators.

For more information, please visit the link below ..

https://community.cadence.com/cadence_blogs_8/b/fv/posts/xcelium-simulator-provides-3x-performance-increase-for-fpga-based-defense-ip-of-streamdsp

감사합니다.