Key Benefits

  • Trusted custom/analog signoff for mature nodes
  • Integrated with Virtuoso AMS/custom design and simulation technologies
  • Decreases overall DRC/LVS signoff iterations with an intuitive Virtuoso platform-based debug environment

Cadence® Assura® Physical Verification supports both interactive and batch operation modes with a single set of design rules. The tool uses hierarchical- and multi-processing for fast, efficient identification and correction of design rule errors. Unique pattern-checking capabilities enable simple rule development and maintenance for hard-to-write rules. Assura Physical Verification is supported where foundry rule decks are available.

Assura Physical Verification reduces overall verification time because it incorporates a fast and intuitive debug capability integrated within the Virtuoso® environment. It facilitates schematic-to-layout cross-probing and incorporates technologies that fix, extract, and compare errors. An interactive short locator accelerates recognition and fixing of shorts. Assura Physical Verification also offers plug-and-play integration with transistor-based Cadence Quantus™ QRC Extraction Solution.