The Cadence® Quantus™ Extraction Solution is the industry’s most trusted signoff parasitic extraction tool. As a single, unified tool, the Quantus solution supports both cell-level and transistor-level extractions during design implementation and signoff. It’s an integral component of our in-design methodology with both the Innovus™Implementation System and Virtuoso® platforms.
The Quantus Extraction Solution is the linchpin that allows designers to do more with Rs and Cs on both digital- and transistor-level flows, assuring on-time tapeout. The Quantus solution has multiple touchpoints throughout the full flow before and after signoff. It’s tightly integrated with the Cadence Genus™ Synthesis Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution and Voltus-Fi Custom Power Integrity Solution, Virtuoso ADE Product Suite, Spectre® Accelerated Parallel Simulator (APS) and eXtensive Partitioning Simulator (XPS), Liberate™Characterization Solution, Legato™ Memory Solution, and Pegasus™ Verification System to allow designers to realize all the benefits listed above.

Our customers trust the Quantus solution and Quantus FS solution for all types of designs. Our new, breakthrough technology in 3D field solver, the Quantus FS solution eliminates the bottleneck of performance by empowering designers to use a 3D field solver to get the accuracy required for advanced-node designs. Providing linear scalability to 1000s of CPUs and foundry certified down to 7nm, the Quantus FS solution is used for: