Xcelium Logic Simulation
Industry-leading simulation for best verification throughput
- Compile/build performance
- Automated parallel and incremental build
- Regression throughput
- Throughput from some single-core performance (including gate-level, RTL, and SV testbench)
- Throughput and productivity improvement with save/restore
- Faster regressions with machine learning
- Reduced latency
- Multi-core performance for long-pole tests
- Native support for advanced use cases
- X-propagation, low-power (UPF/CPF), mixed-signal, and constrained random
- Support for multiple compute platforms
- Supported on x86 and Arm servers
- Supported on the cloud
Cadence® Xcelium™ Logic Simulation provides best-in-class core engine performance for SystemVerilog, VHDL, SystemC®, e, UVM, mixed signal, low power, and X-propagation. It leverages single-core and multi-core simulation technology for best individual test performance and machine learning-optimized regression technology for best regression throughput.
Xcelium single-core simulation delivers best-in-class compile, performance, and throughput with compute platform flexibility, providing:
- Continuous performance optimizations for new design styles and latest coding practices
- Up to 10X compile speedup with Xcelium incremental and parallel builds
- Throughput efficiency using save/restore with dynamic test reload
- Platform support for x86, Arm®, and cloud compute platforms
Xcelium multi-core simulation is for the long-pole tests in your regression. Xcelium simulation integrates multi-core technology to reduce throughput latency, providing:
- Up to 2X performance boost for RTL-directed tests
- Up to 10X performance boost for gate-level ATPG and BIST tests, both zero delay and SDF annotated
Xcelium Logic Simulation with machine learning technology (Xcelium ML) provides machine learning-optimized regression. It makes randomized regressions faster by instructing the Xcelium simulation kernel and offers:
- Up to 5X regression efficiency with similar coverage
- User-directed regression goals, such as maximum throughput, stress design instances, and replacing directed tests with randomized tests
Cadence has been at the forefront on low-power technology, introducing CPF in 2005 and also supporting UPF introduced in 2006 and transitioned to IEEE 1801 in 2009. Xcelium simulation supports both CPF and UPF/IEEE 1801 for low-power simulation.
The Xcelium simulator with mixed-signal option covers advanced digital features such as UVM, SystemVerilog Testbench, UPF/CPF, and SystemC. It also supports the simulation of languages such as Verilog-A, Verilog-AMS, VHDL-AMS, SystemVerilog Real Number Modeling (SVRNM), SystemVerilog, and mixed-signal features along with SPICE, and other digital-centric mixed-signal technologies, such as low power and mixed signal, code coverage and mixed signal, functional safety and mixed signal, and incremental elaboration and mixed signal.
Cadence simulators have been the leaders of constrained random technology and methodology, starting with Specman® Simulation and later being the key driver behind UVM methodology and library standardization. Xcelium constraint solvers are the latest generation of the technology and include a powerful new constraint analyzer and constraint-solving performance-profiling tool.
X-propagation is a feature that avoids X-optimism in LRM-compliant RTL simulation. This allows for early detection of X issues and avoids surprises later in gate-level simulations. Xcelium simulation supports two modes for X-propagation. There is the more pessimistic Forward-Only-X (FOX) mode and less pessimistic Compute-As-Ternary (CAT) mode.