Key Benefits

  • Reduces the risk of silicon re-spins by providing complete verification coverage
  • Detects low-power implementation errors early in the design cycle
  • Verifies multi-million-gate designs much faster than traditional gate-level simulation
  • Closes the RTL-to-layout verification gap using low-power equivalence checking
  • Decreases the risk of missing critical bugs through independent verification technology
  • Enables power intent creation and integration, without having to become a power format expert

Cadence® Conformal® Low Power enables the creation and validation of power intent in the context of a design. Conformal technology combines low-power equivalence checking with structural and functional checks to enable full-chip verification of power-efficient designs.

Optimizing designs for leakage and dynamic power helps designers reduce energy consumption and packaging costs. These advanced low-power design methods can also complicate the verification task, introducing risk during synthesis and physical implementation.

Full-chip, gate-level simulation is not a practical or scalable methodology for verifying today’s large, complex designs. Conformal low power enables designers to create power intent, then verify and debug multi-million-gate designs without simulating test vectors. It combines low-power structural and functional checks with world-class equivalence checking to provide superior performance, capacity, and ease of use.