Automated validation and refinement of timing constraints, from RTL to layout

Encounter Conformal Constraint Designer ensures that timing constraints are valid throughout the entire design process. It identifies issues with clock-domain crossings early on, helping designers achieve convergence on design goals.

Validating, and modifying the constraints necessary for design implementation has conventionally involved manual and error-prone processes, increasing the risk of bad silicon. Validating clock-domain crossings (CDCs) typically requires challenging setup and detailed knowledge of clock propagation. As an increasing number of IP blocks come together in a design, each with its own timing constraints and set of clocks, the risk of an un-verified SoC ending in silicon failure also grows. Encounter® Conformal® Constraint Designer provides the most complete and efficient path to develop and manage constraints and CDCs, ensuring they are functionally correct—from RTL to layout. By pinpointing real design issues quickly and accurately, delivering higher-quality timing constraints, and finding issues with clock domain synchronizers, it allows designers to reduce overall design cycle times and enhance quality of silicon in complex SoC designs.


  • Ensures timing constraints are correct and complete
  • Shortens design cycles with a comprehensive analysis environment that checks the creation and integration of block-level and top-level constraints
  • Validates that CDCs have proper synchronizers in place, easily visualized through a FIFO manager
  • Reduces the risk of re-spins through formal validation of constraints
  • Speeds convergence for timing closure by quickly validating failing timing paths as functionally false
  • Creates initial constraints effortlessly with the SDC Advisor