Global synthesis that enables concurrent optimization of timing, area, and power intent

Encounter® RTL Compiler offers a unique set of patented global-focus algorithms that perform true top-down global RTL design synthesis to accelerate silicon realization. With concurrent multi-objective optimization (timing, area, and power intent) and support for advanced low-power design techniques, Encounter RTL Compiler reduces chip power consumption while meeting frequency goals.

rtl_compilerWith its combination of breakthrough algorithms, efficient data structures, and modern programming techniques, Encounter RTL Compiler delivers the best speed, area, and power after physical implementation for the most challenging designs. New advanced,production-proven, global synthesis technology further improves these results while delivering even faster runtimes. At the core of Encounter RTL Compiler is a breakthrough synthesis algorithm—global mapping. This technique devotes more time to examining the overall solution space to deliver an optimized netlist for meeting your design intent goals throughout physical design.

Encounter RTL Compiler performs multi-objective optimization that simultaneously considers timing, power, and area intent to create logic structures that converge on all these goals in a single pass.


  • A well-balanced logic structure isolates critical paths, reduces power, area, and congestion in off-critical logic, and enables faster timing closure and design convergence through placement and routing
  • Spatial technology eliminates the need for wireload models by modeling physical interconnect at a higher level of abstraction for use in register-transfer level (RTL)-to-gate optimization
  • Encounter RTL Compiler Advanced Physical Option incorporates Encounter Digital Implementation System placement technology into synthesis, providing real physical timing to logic structuring, mapping, optimization, and analysis
  • Encounter RTL Compiler Low Power Option reduces power consumption through single-pass multi-Vt optimization, hierarchical and multi-stage clock gating, true top-down multi-supply voltage exploration and synthesis, RTL power estimation, and full power shutoff support with the Common Power Format (CPF)
  • Multi-bit cell inferencing allows for the merging of single registers into mutli-bit registers (when available in a target library) to share clock enables and low overall chip power
  • Shrinks die sizes with multi-objective optimization, which creates smaller logic structures for non-timing-critical regions
  • Multi-mode synthesis optimization and analysis accelerates overall turnaround time to design closure for complex chips with multiple functional modes
  • Superthreading technology leads to superior runtimes, quicker turnaround times, and faster convergence on design goals
  • Superior capacity increases productivity by enabling chip-level synthesis and eliminating manual partitioning, budgeting, and reassembly
  • A built-in design quality analyzer identifies pre-synthesis design issues that may lead to sub-optimal or unintended results
  • Is easy to adopt—uses standard inputs and outputs so that, if you require improved quality of silicon (timing, area and power after wires), you can get en route quickly to achieving your design goals