Design rule checking and layout vs. schematic verification
The DRC/LVS tool of choice for custom, AMS, and RF designers, Assura Physical Verification ensures high-yielding custom IP for nanometer SoC designs.
Cadence® Assura® Physical Verification supports both interactive and batch operation modes with a single set of design rules. It uses hierarchical processing and multi-processing for fast, efficient identification and correction of design rule errors. Unique pattern-checking capabilities enable simple rule development and maintenance for hard-to-write rules. Assura Physical Verification incorporates advanced sub-65nm process parameter measurement, nanometer design rules for DFM, and process design rule checks.
Assura Physical Verification reduces overall verification time because it incorporates a fast and intuitive debug capability integrated within the Virtuoso® custom design environment. It facilitates schematic-to-layout cross-probing and incorporates technologies that fix, extract, and compare errors. An interactive short locator accelerates recognition and fixing of shorts. Assura Physical Verification also offers plug-and-play integration with transistor-based Cadence QRC Extraction technology.
- Trusted at more than 300 companies worldwide
- Integrates with Virtuoso AMS/custom design and simulation technologies
- Decreases overall DRC/LVS and rework cycle via an intuitive Virtuoso-based debug environment
- Integrates with the leading transistor-based parasitic extraction flow (Cadence QRC Extraction/Assura RCX transistor-based parasitic extraction)