Scalable, Coherent On-Chip Network IP
Existing hardware-based coherency solutions have two key limitations on performance and scalability. First, coherency systems are usually fixed configurations, which means they cannot adapt to your system requirements. They may be over-designed or under-performing. Second, to manage the complex on-chip communications, they employ separate interconnects for coherent and non-coherent traffic. This creates unnecessary floor planning obstacles, prevents efficient resource sharing, requires multiple interconnect methodologies, and requires additional hardware support to allow the traffic to interact.
NetSpeed Gemini effectively addresses these needs. It is a high-performance, scalable, coherent On-Chip Network IP solution. It supports all three levels of coherent traffic – cache coherent, I/O coherent & non-coherent traffic – in a single on-chip network. NetSpeed Gemini provides full cache coherency for small and large SoC designs. NetSpeed Gemini delivers high performance and significant time-to-market advantages to SoC designers for a wide range of markets from mobile, networking to high-performance computing.
Higher Performance, Faster Time-to-market, Lower Power
NetSpeed Gemini’s unique architecture allows it to scale performance to match increasing coherency bandwidth. This allows NetSpeed Gemini to be used as NoC platform for entire product families
Existing coherency solutions are fixed-point solutions leading to system designs that may be under-performing and over-performing. However, NetSpeed Gemini is a fully configurable and customizable coherent NoC IP. NetSpeed Gemini is configured and optimized using NocStudio – a NoC architecture exploration platform. In a user controlled and automated design environment, a number of coherency design choices can be rapidly generated, evaluated and benchmarked.
Flexible, Scalable Solution
NetSpeed Gemini supports multiple levels of SoC traffic: cache coherent, I/O coherent, and non-coherent traffic.
It is a directory-based coherency solution and automatically increases the number of coherency module & directories needed to support the SoC and coherency bandwidth needs.
Algorithmic, Sophisticated NoC
NetSpeed Gemini uses sophisticated algorithms to solve complex SoC issues like QoS & deadlock avoidance.
It presents elegant solutions to tradeoffs between performance metrics like bandwidth, latency & power.
Power Efficient NoC
NetSpeed Gemini is efficient in handling power, performance tradeoffs prevalent in SoC designs.
It packetizes data and performs traffic-based optimizations optimizing every router, buffer and wire in the NoC.
It also provides SoC architects with advanced low-power techniques like activity-based clock gating & power islanding.
Higher Performance, Faster Time-to-market, Lower Power, Scalable Solution
Tbps of on-chip bandwidth
The underlying hardware elements, like the coherency controller, coherency directory & NoC router, are designed for supporting higher throughput – Terabits per second – with low footprint. Using these elements, efficient NoC can be built for variety of SoCs – from mobile to enterprise computing & networking.
NetSpeed Gemini bridges the front-end & back-end design gap. It allows for more design iterations & refinement throughout design cycle. NetSpeed Gemini is also correct by construction, significantly reducing debug time.
NetSpeed Gemini’s optimizations architecturally reduce power in NoC. It uses packetized data for communication reducing number of wires. It supports activity-based clock gating & power islanding.
NoC Solution Platform
NetSpeed Gemini’s innovative and patent-pending directory structure allows it to deliver scalable high performance with increasing number of IP blocks in a SoC. This allows for Gemini to be used as a NoC platform for an entire product family.
NetSpeed NocStudio – Architecture Exploration Platform
NocStudio enables SoC architects to design, configure & simulate NetSpeed’s NoC IP as well as evaluate multiple SoC architectures.
NocStudio provides a new level of automation in designing SoC interconnects – right from determining the most efficient topology to automating optimization of NoC channels, buffers & routing for system level user specifications.
NocStudio takes high level SoC specifications like number of components, physical floorplan of SoC, performance (bandwidth, latency), coherency requirements (coherency bandwidth, level of coherency participation, protocol type), QoS and power.
NocStudio performs multiple optimizations to construct NoC. Based on the specifications, it optimizes NoC topology, routing between the blocks, channel & link allocation as well as make suggestions on alternate placement. It automatically creates the appropriate number of coherency controllers and coherency directory needed. It also provides a high degree of user interaction to allow customization of the NoC.
The final step in the design flow is used to generate synthesizable RTL along with functional C++ models, detailed performance statistics and sanity verification test benches.